1. Field of the Invention
The present invention generally relates to a semiconductor device having the function of measuring various capacitances such as a wiring capacitance, a gate capacitance and a junction capacitance, and more particularly to a semiconductor device having a circuit for CBCM (Charge Based Capacitance Measurement) using a CBCM method as a capacitance measuring method.
2. Description of the Background Art                (Principle of CBCM Method)        
FIG. 33 is a circuit diagram showing a structure of a circuit for CBCM in a semiconductor device employing a conventional CBCM method. As shown in FIG. 33, a PMOS transistor MP1 and an NMOS transistor MN1 are connected in series, and a PMOS transistor MP2 and an NMOS transistor MN2 are connected in series. A source of the PMOS transistor MP1 is connected to a pad 52 and a source of the PMOS transistor MP2 is connected to a pad 54, and sources of the NMOS transistors MN1 and MN2 are connected to a pad 55 in common. Moreover, a pad 53 is connected to gates of the PMOS transistors MP1 and MP2 and a pad 51 is connected to a well region to be a back gate, and a pad 56 is connected to gates of the NMOS transistors MN1 and MN2.
Furthermore, an electric potential NW, a reference potential Ref, a PMOS gate potential Gp, a test potential Tst, an electric potential Gnd and an NMOS gate potential Gn are applied to the pads 51, 52, 53, 54, 55 and 56, respectively. The electric potential NW is used for setting an electric potential in well regions of the PMOS transistors MP1 and MP2, and the electric potential Gnd gives an electric potential to active regions (not shown) and the sources in the NMOS transistors MN1 and MN2.
The PMOS transistors MP1 and MP2 and the NMOS transistors MN1 and MN2 make pairs having gate lengths, gate widths and gate insulating film thicknesses which are equal to each other.
A reference capacitance Cref (capacitance value=Cm (dummy capacitance)) is provided between a drain (node N1) and the source in the NMOS transistor MN1, and a test capacitance Ctst (capacitance value=Cm+Ct (target capacitance)) is provided between a drain (node N2) and the source in the NMOS transistor MN2. The circuit for CBCM shown in FIG. 33 has an object to measure the target capacitance Ct.
FIG. 34 is a timing chart showing an operation of the circuit for CBCM illustrated in FIG. 33. An operation for measuring a capacitance value of a conventional circuit for CBCM will be described below with reference to FIG. 34.
As shown in FIG. 34, the reference potential Ref, the test potential Tst and the electric potential NW are fixed to a power supply potential Vdd, and the electric potential Gnd is fixed to a ground potential Vss. Input voltage waveforms of the PMOS gate potential Gp and the NMOS gate potential Gn are applied to turn ON one of the NMOS transistors MN1 and MN2 and the PMOS transistors MP1 and MP2 at any time. At the same time, accordingly, a through current flowing from the PMOS transistor MP1 to the NMOS transistor MN1 or from the PMOS transistor MP2 to the NMOS transistor MN2 is not generated.
As shown in FIG. 34, the PMOS transistors MP1 and MP2 are turned ON to supply currents I1 and I2 from the pads 52 and 54, thereby charging the reference capacitance Cref and the test capacitance Ctst for a time t1 to t2. In the meantime, both of the NMOS transistors MN1 and MN2 are set in an OFF state. Therefore, electric potentials of the nodes N1 and N2 connected to the reference capacitance Cref and the test capacitance Ctst reach the power supply potential Vdd.
For a time t2 to t3, all of the PMOS transistors MP1 and MP2 and the NMOS transistors MN1 and MN2 are turned OFF. Ideally, electric charges applied to the reference capacitance Cref and the test capacitance Ctst are held. Therefore, the electric potentials of the nodes N1 and N2 maintain the power supply potential Vdd.
For a time t3 to t4, only the NMOS transistors MN1 and MN2 are turned ON. Therefore, the electric charges applied to the reference capacitance Cref and the test capacitance Ctst are discharged from the pad 56 so that the electric potentials of the nodes N1 and N2 reach the ground potential Vss.
For a time t4 to t5, all of the MOS transistors are turned OFF. Ideally, the reference capacitance Cref and the test capacitance Ctst maintain the ground potential Vss which is obtained when the discharge is completed.
The above-mentioned operation is set to be one period T (a time from t1 to t5), and subsequently, this operation is repeated. Time mean values of the currents I1 and I2 are observed by a measuring device. The following equation (1) is established, wherein a frequency of a gate input waveform (Gp, Gn) is represented by f(=1/T).                                                                         I2                -                I1                            =                                                                    Ctst                    ×                    Vdd                                    T                                -                                                      Cref                    ×                    Vdd                                    T                                                                                                        =                                                                    (                                          Cm                      +                      Ct                      -                      Cm                                        )                                    ×                  Vdd                                T                                                                                        =                              Ct                ×                Vdd                ×                f                                                                        (        1        )            
Accordingly, a target capacitance value Ct is obtained by the following equation (2).                     Ct        =                              I2            -            I1                                Vdd            ×            f                                              (        2        )            
The CBCM method has an advantage that a dummy capacitance (a parasitic capacitance) Cm can be cancelled as shown in the equation (1), thereby obtaining a desirable target capacitance Ct.
(Error Factor of CBCM Method)
The error factor of the CBCM method includes 1) precision in a measuring device, 2) a leak component of a transistor which is in an OFF state, and 3) a mismatch of transistors making a pair. The items 2) and 3) will be described below in detail.
2) FIG. 35 is a chart showing a fluctuation in an electric potential which is caused by an offleak of a transistor. FIG. 35 shows a part of the timing chart in FIG. 34 (Gp (solid line), Gn (dotted line), and N1 and N2) which is enlarged.
As shown in FIG. 35, the NMOS transistors MN1 and MN2 are turned ON for a time t3 to t4 so that the electric potentials of the nodes N1 and N2 reach the ground potential Vss. At a time t4 to t5, then, all of the PMOS transistors MP1 and MP2 and the NMOS transistors MN1 and MN2 are turned OFF.
Ideally, the offleak current is not generated. Therefore, the electric potentials of the nodes N1 and N2 are held in the ground potential Vss and the offleak current is actually present. When the amount of electric charges held in the reference capacitance Cref and the test capacitance Ctst is decreased by the amount of electric charges given with the offleak current for the time t4 to t5, the electric potentials of the nodes N1 and N2 rise by a fluctuation ΔVS2 in an electric potential during a standby from the ground potential Vss as shown in FIG. 35. A fluctuation ΔVS1 in an electric potential in the standby state indicates a reduction in the electric potential from the power supply potential Vdd.
Such a phenomenon is remarkable when the reference capacitance Cref and the test capacitance Ctst are in order of 0.01 fF to 1 pF. After the time t5, accordingly, charging is not carried out with a potential difference of the power supply potential Vdd but with a potential difference of Ve(=Vdd−ΔVS2) due to the rise. Since the capacitance values connected to the nodes N1 and N2 are different from each other, a value of the potential difference Ve is also varied between the nodes N1 and N2. In order to calculate a portion having the potential difference Ve with the power supply potential Vdd by the equation (2), an estimation of the target capacitance Ct is measured to be smaller. More specifically, it is implied that a fluctuation in the electric potentials of the nodes N1 and N2 which are caused by an offleak causes a measurement error.
3) The mismatch of the transistors making a pair implies that a threshold voltage, a drain current, a gate offleak current, a gate tunnel current, a junction capacitance, a gate overlap capacitance and the like are changed due to a variation in a process even if the PMOS transistors MP1 and MP2 and the NMOS transistors MN1 and MN2 have the same sizes on masks, respectively. As indicated in the equation (2), the target capacitance Ct is measured by utilizing a difference in currents of the transistors making a pair. Therefore, the identity of electric characteristics of the transistors making a pair determine measuring precision.
As shown in FIG. 35, the NMOS transistors MN1 and MN2 are turned ON and the electric charges stored in the reference capacitance Cref and the test capacitance Ctst are discharged. Then, when all of the PMOS transistors MP1 and MP2 and the NMOS transistors MN1 and MN2 are OFF in the standby state, the electric potentials of the nodes N1 and N2 rise by the influence of the gate offleak current. Consequently, there is a problem in that the measuring precision in the target capacitance Ct is reduced.
Moreover, the gate length and the gate insulating film thickness of the transistor tend to be reduced due to high integration. When a gate insulating film formed by a silicon oxide film or a silicon oxide nitride film has a thickness of approximately 2 nm, there is observed a gate tunnel phenomenon in which electrons or holes tunnel through the gate insulating film while they run over a channel from a source to reach a drain. When the transistor is ON, tunneling from a source region having the greatest potential difference from a gate voltage is carried out more often. When the transistor is OFF, the tunneling from a drain region is carried out more often. A gate tunnel current is observed as a gate current. If the gate tunnel current is generated, a drain current is decreased during ON and a gate-off current is increased during OFF as compared with the case in which the tunnel current is not generated. Accordingly, even if the thickness of the gate insulating film is reduced, an increase in the drain current during ON cannot be expected. By using a transistor including a gate insulating film having a thickness of approximately 2 nm for the CBCM method, there is a problem in that the same phenomenon as that in FIG. 35 occurs to reduce the measuring precision in the target capacitance Ct because a gate offleak is great.